Technical Field
The present disclosure relates to a frequency control circuit, a frequency control method and a phase locked loop circuit. More particularly, the present disclosure relates to a frequency control circuit, which does not need to utilize additional clock signals for controlling the frequency of the output signal, and a frequency control method and a phase locked loop circuit.
Description of Related Art
A phase locked loop circuit (PLL) is a control system that utilizes a negative feedback to generate an output signal, which is phase-locked to an input signal. The phase locked loop circuit is widely used in a variety of applications, such as synthesizing a stable frequency or recovering a signal from a communication channel.
Phase locked loop has been widely used in communication system to perform clock and data recovery. Generally, the phase locked loop circuit needs to have an additional clock signal for a frequency tracking loop thereof, and the additional clock signal can be received from a transmitter or created by a on chip high accuracy reference clock generator. The clock reference that from transmitter needs to have another channel; on chip high accuracy reference clock generator usually suffer from high power consumption. Extract the frequency information directly from random data stream is another way to provide frequency locked in PLL. However, there are ISI jitters commonly existed due to the channel loss in the random data input signal. Therefore, how to prevent the jitters of the input signal from affecting the operation of the phase locked loop circuit is also an important issue.